TSMC, the Taiwan-based chip manufacturer, detailed its development timeline during its 2022 TSMC Technology Symposium and plans to introduce its 3nm chips by the second half of this year and its 2nm chips by the year 2025.
Furthermore, The 3nm node will consist of 5 tiers where each tier is more powerful, more transistor-dense, and more efficient which the manufacturer labeled as N3, N3E (Enhanced), N3P (Performance Enhanced), N3S (Density Enhanced) with the last one called N3X (Ultra-high Performance).
The 2nm (N2) chip, on the other hand, will boost performance by 10 to 15% at the same power draw and will also bring a 25% to 30% reduction in power consumption at the same frequency and transistor count compared to the N3 node. The N2 has an increased density of 1.1x the density of the N3 node.
Lastly, the new nanosheet transistors, which TSMC introduced and are called GAAFETs (gate-all-around field-effect transistors), will increase performance per watt by reducing resistance.
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